[DE2-115] Lab.5-1: UART transmitter

[UART : Universal Asynchronous Receiver-Transmitter]

 

DE2-115 보드를 이용하여 시리얼 통신을 실습한다.  

 

baudrate: 300, 600, 1200, 2400, 4800, 9600, 14400, 19200, 28800, 31250, 38400, 57600, and 115200

data frame

 

[rs232.v]

UART Transmitter 를 Verilog 로 기술한다.  

/////----------------------------------------/////
module rs232(
    input               clk, 
    input               rst_n, 
    
    input               tx_en, 
    output              tx, 
    
    input   [7:0]       din
);


    // 50Mhz / 115200 = 434.0
    parameter           bit_rate = 434; 
    parameter           bit_boundary = 217; 
    
    
    reg     [1:0]       tx_state; 
    reg     [8:0]       tx_cnt; 
    reg     [2:0]       tx_data_cnt; 
    reg     [7:0]       tx_data; 
    reg                 txd; 			
/////----------------------------------------/////
    always @(posedge clk, negedge rst_n) begin
        if (rst_n == 0) begin
            tx_state	<= 2'b00; 
        end
        else begin
            case (tx_state)
                2'b00	: begin
                    if (tx_en == 1'b1)
                        tx_state	<= 2'b01; 
                end
                2'b01	: begin
                    if (tx_cnt == bit_rate)
                        tx_state	<= 2'b10; 
                end
                2'b10	: begin
                    if (tx_cnt == bit_rate && tx_data_cnt == 3'b111)
                        tx_state	<= 2'b11; 	
                end
                2'b11	: begin
                    if (tx_cnt == bit_boundary)
                        tx_state	<= 2'b00; 
                end
            endcase 
        end
    end

/////----------------------------------------/////
    always @(posedge clk, negedge rst_n) begin
        if (rst_n == 0) begin
            tx_cnt	<= 9'd0; 
        end
        else begin
            if (tx_state == 2'b00 || tx_cnt == bit_rate)
                tx_cnt	<= 9'd0;
            else
                tx_cnt	<= tx_cnt + 1'b1;
        end
    end

/////----------------------------------------/////
    always @(posedge clk, negedge rst_n) begin
        if (rst_n == 0) begin
            tx_data_cnt	<= 3'd0; 
        end
        else begin
            if (tx_state == 2'b10) begin
                if (tx_cnt == bit_rate) 
                    tx_data_cnt	<= tx_data_cnt + 1'b1;
            end
            else begin
                tx_data_cnt	<= 3'd0;
            end 
        end
    end

/////--------------------------------------------------/////
    always @(posedge clk, negedge rst_n) begin
        if (rst_n == 0) begin
            tx_data	<= 8'd0; 
        end
        else begin
            if (tx_state == 2'b00 && tx_en == 1) 
                tx_data	<= din; 
        end
    end


    assign tx = txd;
/////----------------------------------------/////
    always @(posedge clk, negedge rst_n) begin
        if (rst_n == 0) begin
            txd	<= 1'b1; 
        end
        else begin
            if (tx_state == 2'b00) begin 
                txd	<= 1'b1; 
            end
            else if (tx_state == 2'b01) begin 
                txd	<= 1'b0; 
            end
            else if (tx_state == 2'b10) begin 
                case (tx_data_cnt)
                    3'd0	: txd	<= tx_data[0]; 
                    3'd1	: txd	<= tx_data[1]; 
                    3'd2	: txd	<= tx_data[2]; 
                    3'd3	: txd	<= tx_data[3]; 
                    3'd4	: txd	<= tx_data[4]; 
                    3'd5	: txd	<= tx_data[5]; 
                    3'd6	: txd	<= tx_data[6]; 
                    3'd7	: txd	<= tx_data[7]; 
                endcase
            end
            else begin
                txd	<= 1'b1; 
            end
        end
    end

endmodule

 

[Pin Assign]

 

[PuTTy]

시리얼 터미널 프로그램을 이용하여 시리얼 포트와 연결한다.  

  - PC 관리자에서 Serial Port Number 을 확인한다. 

  - Putty 를 실행하고 설정한다. 

      Baudlate: 115200

      Flow Control: None

012

 

[Test Result]

이를 합성 후 출력결과를 시리얼 모니터로 확인한다. 

 

 

[참조] 

www.chiark.greenend.org.uk/~sgtatham/putty/latest.html