본문 바로가기

원s/RTL

[RTL] HW Verification

Verilog Coding Guideline

 

[Register Transfer Level modeling]

  • Must code at register transfer level

 

HW Verification

 

Algorithm

  • An algorithm is a series of mathematical steps which will give you the answer to a particular kind of problem.
  • Algorithm verification with Python: debugging print(), debugger, try, except

Architecture

 

  • Architecture is the component part set of design

HW descrition

using built-in function

floating-point simulation

fixed-point simulation

'원s > RTL' 카테고리의 다른 글

[Syn] VCS Command  (0) 2021.03.20
[Syn] Synthesis Constrain Command  (0) 2021.03.13