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[function simulation]
더보기
$ ./run_vcs_fsim.tcl
vcs \
-sverilog \
-timescale=1ns/1ns \
+v2k -R -gui \
<tb.v> \
<fun.v> \
-l fsim.log
[timing simulation]
더보기
$ ./run_vcs_tsim.tcl
vcs \
-sverilog \
-full64 \
-reportstats \
-timescale=1ns/1ns \
+define+<MACRO> \
-sdf max:<TOP.DUT>:<syn.sdf> \
-negdelay \
+neg_tchk \
+maxdelays \
+incdir+<PATH> \
+v2k -R -gui \
<tb.v> \
<syn.v> \
<PATH>/<pdk.v> \
-l tsim.log
[참조]
https://solvnet.synopsys.com/
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