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원s/RTL

[Syn] Synthesis Constrain Command

Design Complier Quick Start

 

Synopsys Design Compiler Execute

/// 2020.02.20
$ source <syn.cshrc>
$ dc_shell-xg-t -f <run_syn.tcl>

 

Synthesis Script (run_syn.tcl)

더보기
/// 2020.02.20
> read_verilog <desin.v>
> current_design <module_name>
> check_design -multiple_design
> link 
> uniquify 
 
> set_max_area VALUE 
> set auto_wire_load_selection true 
> set_fix_multiple_port_nets -all -buffer_constants

> set_load VALUE [all_inputs]
> set_load VALUE [all_outputs]

> create_clock -period VALUE -name <clk> [get_ports <clk>]
> set_clock_uncertainty -setup VALUE [get_clocks <clk>]
> set_clock_uncertainty -hold VALUE [get_clocks <clk>]
> set_clock_latency –source -max VALUE [get_clocks <clk>]
> set_clock_transition VALUE [get_clocks <clk>]

> set_input_delay VALUE -clock <clk> [all_inputs]
> remove_input_delay [get_ports <clk>]
> set_output_delay VALUE -clock <clk> [all_outputs]
> set_input_transition -max VALUE [all_inputs]

> set_ideal_network [get_ports <clk>] 
> check_timing
> check_design –multiple_design
> compile_ultra
 
> report_area
> report_design
> report_power
> report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group
 
> write -format verilog -hierarchy -output <syn.v>
> write_sdf -version 1.0 <syn.sdf>
> write_sdc <syn.sdc>
 
> quit

 

 

 

[참조]

https://solvnet.synopsys.com/

 

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