[Verilog] Verilog Introduction

Verilog

VerilogHDL 은 Hardware Description LLanguage로 디지털 시스템을 설계할 수 있다.

Verilog 언어는 하드웨어 기술 시, 다양한 추상화 (Abstraction level)를 제공하여 Behavioral level, Structual level (Gate level), RTL (Register Transfer Level) 등으로 Modeling 이 가능하고, 자동화 툴인 EDA (Electronic Design Automation) Tool을 이용하여 하드웨어를 구현한다.    

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Describes interface and function in verilog

• Module definition
• Declaration of input and output ports and signals
• Module instantiations
• Function descritions

 

 

Combination circuit modeling

• assign: Continuous assignment
• Define each port as input, output, or inout

 

Structual Level Modeling

• Create hierarchy by Instantiation modules
• Connecting module ports to local ports or nets
• Named port connection

 

Behavioral Level Modeling

• always procedure block: Hardware construct
• @(): Procedure resumes when an event in the event list occur
• *: Wildcard operator

 

Testbench

• initial procedure block: Testbench construct
• Executes one at start of simulation
• initial block are NOT synthesizable
• #: delay

 

Register Transfer Level modeling

• Must code at register transfer level
• Register and “transfer” (combinational) logic must be worked out before coding can start
• <=: non-blocking assignment